Low Power Memory Design Using Source Coupled Logic

Design flexibility and power consumption in addition to the cost, have always been the most important issues in design of integrated circuits. Power dissipation and energy consumption are especially important when there is a limited amount of power budget or limited source of energy. Recently advances in VLSI Technology have made it possible to put a complete System on Chip (SOC) which facilitates the developments of PDAs, Laptop, cellular phones etc. The evolutions of these applications profiles power dissipation as a critical parameter in digital VLSI design. Source coupled logic (SCL) applications are another examples where power dissipation is the primary design issue. The objective of this paper is “Low power memory design using source coupled logic”. In this paper, the detailed working operation of the memory architecture has been analyzed. The Memory cell design is implemented in 0.18 micron CMOS process technology in both schematic mode and symbol mode. After implementing the memory cell, power analysis by varying parameters like temperature, supply voltage, capacitance and frequency has been done. Keywords--CMOS, Integrated circuit, Dynamic power, NMOS, Static power, VLSI.